The present exemplary embodiments relate to semiconductor substrates that have through silicon vias and, more particularly, relate to the formation of capture pads in contact with the through silicon vias that enhance the current spreading ability of the capture pad.
Three-dimensional (3D) stacking of semiconductor chips promises higher transistor densities and smaller footprints of electronic products. 3D stacking is a single package containing a vertical stack of semiconductor chips which are interconnected by means of through silicon vias (TSVs). 3D stacking based on TSVs offers the benefits of more functionality, higher bandwidth and performance at smaller sizes, alongside lower power consumption and cost, even in an era in which conventional feature-size scaling becomes increasingly difficult and expensive. TSVs provide an electrical connection from the active front-side (face) of a semiconductor chip through the semiconductor substrate to the back-side of the substrate. TSVs allow a semiconductor chip or wafer to be vertically interconnected to another semiconductor chip or wafer. TSVs also allow the interconnection of multiple vertically stacked semiconductor chips or wafers with each other.